Hall electromotive force signal detection circuit and current sensor thereof

ABSTRACT

The present invention relates to a hall electromotive force signal detection circuit and a current sensor thereof each of which is able to achieve excellent wide-band characteristics and fast response as well as high accuracy. A difference calculation circuit ( 15 ) samples a component synchronous with a chopper clock generated by a chopper clock generation circuit ( 14 ), out of an output voltage signal of a signal amplifier circuit ( 13 ), at a timing obtained from the chopper clock, so as to detect the component. An integrating circuit ( 16 ) integrates an output from the difference calculation circuit ( 15 ) in the time domain. An output voltage signal from the integrating circuit ( 16 ) is fed back to a signal amplifier circuit ( 13 ) via a third transconductance element ( 17 ).

TECHNICAL FIELD

The present invention relates to a hall electromotive force signaldetection circuit and a current sensor thereof, and more specifically,to a hall electromotive force signal detection circuit and a currentsensor thereof each of which can achieve wide-band characteristics andfast response as well as high accuracy in a magnetic sensor using a hallelement, such as a current sensor.

BACKGROUND ART

A magnetic sensor using a hall element is widely used not only as aproximity sensor, a linear position sensor, a rotation angle sensor, orthe like, each of which is a sensor for detecting positional informationof a magnet, but also as a current sensor for measuring, in anon-contact manner, the amount of current flowing in a current conductorby detecting a magnetic field induced by the current flowing in thecurrent conductor.

Particularly, it is required for the current sensor used to detect aninverter current of a motor, to highly precisely detect the invertercurrent that is switched at a high-speed frequency, for the purpose ofimproving the efficiency of motor control.

Since the hall element has a magnetoelectric conversion function togenerate a hall electromotive force signal depending on an intensity ofan input magnetic field, the hall element is widely used as a magneticsensor. However an offset voltage (unbalanced voltage) exists in thehall element. The offset voltage is a non-zero finite voltage and isoutput even in a state where the magnetic field is zero, i.e., in astate of no magnetic field.

In view of this, in regard to the magnetic sensor using a hall element,in order to cancel an offset voltage of the hall element, there is adriving method for the hall element, which is generally known asspinning current method or connection commutation method. In thismethod, switching between a position of a terminal pair for flowing adriving current to the hall element and a position of a terminal pairfor detecting a hall electromotive force signal is periodicallyperformed synchronized with clock called chopper clock (see, forexample, Non Patent Document 1).

The spinning current method for the purpose of cancelling the offsetvoltage is configurable by use of a switching circuit in a CMOSsemiconductor circuit, and therefore, a hall electromotive forcedetecting circuit to realize a highly-accurate magnetic sensor generallyincludes a switching circuit in order to implement the spinning currentmethod.

Further, since a hall electromotive force signal generated in the hallelement is generally feeble, the hall electromotive force signaldetection circuit includes an signal amplifier circuit so as to amplifythe hall electromotive force signal. Here, in a case where there is afinite offset voltage in this signal amplifier circuit, it is alsonecessary to perform the offset cancellation of the offset voltageincluded in the signal amplifier circuit.

Under these circumstances, as for the hall electromotive force signaldetection circuit for detecting and amplifying the hall electromotiveforce generated by the hall element, there has been a known circuitconfiguration of signal amplifier circuit using a current feedbackamplifier circuit that is suitable for the combination with the spinningcurrent method of the hall element. Among these current feedbackamplifiers, the circuit configuration in which the offset voltage of theamplifier circuit is modulated by using a chopper clock to the chopperclock frequency is generally known as chopper amplifier.

It is known that, with the use of a hall electromotive force detectingcircuit in which the circuit for implementing the spinning currentmethod in the hall element is combined with the circuit configuration ofthe chopper amplifier in the signal amplifier circuit, it is possible tomodulate both the offset voltage of the hall element and the offsetvoltage of the signal amplifier circuit at the frequency of the chopperclock (see, for example, Patent Document 1 and Non Patent Document 2).

The offset cancellation of the hall element by the spinning currentmethod is described below.

FIGS. 1A and 1B illustrate the hall electromotive force detection at thetime when the direction of the driving current biasing the hall elementis switched between 0 degree and 90 degrees every time the phase of thechopper clock is switched between two values, i.e., φ1 and φ2. FIG. 1Aillustrates a case where the phase of the chopper clock is φ1 and thedriving direction of the hall element is 0 degree, and FIG. 1Billustrates a case where the phase of the chopper clock is φ2 and thedriving direction of the hall element is 90 degrees. Note that the hallelement is modeled as a four-terminal element including four resistors,and is driven by a constant current.

In FIGS. 1A and 1B, when the driving direction of the hall element isswitched between 0 degree and 90 degrees, voltage signals Vhall (φ1) andVhall (φ2) measured in the hall element are represented as the sum ofthe hall electromotive force signal Vsig(B) corresponding to the targetmagnetic field B to be detected by the magnetic sensor using the hallelement and the offset voltage Vos (Hall) of the hall element, asrepresented by Expression 1.

By periodically switching the direction of a bias current of the hallelement between 0 degree and 90 degrees synchronized with the chopperclock, it is possible to switch the polarity of the hall electromotiveforce signal Vsig (B) corresponding to the target magnetic field to bedetected between inverted polarity and non-inverted polarity, therebymaking it possible to perform frequency modulation of the hallelectromotive force signal Vsig(B) corresponding to the target magneticfield to be detected, at the frequency f_chop of the chopper clock. Onthe other hand, as for the DC offset voltage Vos(Hall) of the hallelement, even if the driving direction of the hall element is switchedbetween 0 degree and 90 degrees, the DC offset Vos (Hall) retains itspolarity. Therefore, Vos(Hall) is not frequency-modulated by the chopperclock.

$\begin{matrix}\left\lbrack {{Math}.\mspace{14mu} 1} \right\rbrack & \; \\{{Signals}\mspace{14mu} {Generated}\mspace{14mu} {in}\mspace{14mu} {the}\mspace{14mu} {Hall}\mspace{14mu} {Element}\mspace{14mu} \left\{ \begin{matrix}{{{Vhall}\mspace{11mu} \left( {\varphi \; 1} \right)} = {{+ {{Vsig}(B)}} + {{Vos}({Hall})}}} & \left( {{{Chopper}\mspace{14mu} {Clock}} = {\varphi 1}} \right) \\{{{Vhall}\mspace{11mu} ({\varphi 2})} = {{- {{Vsig}(B)}} + {{Vos}({Hall})}}} & \left( {{{Chopper}\mspace{14mu} {Clock}} = {\varphi 2}} \right)\end{matrix} \right.} & {{Expression}\mspace{14mu} 1}\end{matrix}$

Based on the foregoing, in a case where the driving current of the hallelement is switched between 0 degree and 90 degrees synchronized withthe chopper clock, the signal Vhall generated in the hall elementexhibits a waveform as illustrated in FIGS. 2A to 2D. Further, thespectrum of the signal generated in the hall element exhibits a spectrumas illustrated in FIG. 3. Accordingly, it is understood that the hallelectromotive force signal Vsig(B) corresponding to the target magneticfield to be detected and the offset voltage Vos(Hall) of the hallelement are separated in the frequency domain. This is the principle ofthe offset cancellation using the spinning current method.

It is noted that the above description deals with an example in whichthe driving direction of the hall element having four terminals isswitched between two directions, i.e., 0 degree and 90 degrees.Similarly, when the driving direction of the hall element is switchedamong four directions, i.e., 0 degree, 90 degrees, 180 degrees, and 270degrees, it is also possible to separate the hall electromotive forcesignal and the offset voltage in the frequency domain.

Furthermore, a technique described in Patent Document 2 relates to ahall electromotive force signal detecting apparatus which is able toeffectively minimize a pattern noise generated in a ΔΣ modulator used todetect a hall electromotive force signal of a hall element. Furthermore,a technique described in Patent Document 3 relates to a hallelectromotive force signal detecting apparatus which performs a signalprocessing by use of a ΔΣ modulator and which is able to effectivelyminimize settling errors.

Furthermore, a technique described in Patent Document 4 relates to acurrent sensor, and discloses a method for reducing ripple-shaped noiseby use of a filter called a Notch filter or a COMB filter having a zeropoint at the frequency of a chopper clock, in association with a circuittechnique called chopper amplifier.

Furthermore, a technique described in Patent Document 5 relates to achopper stabilized amplifier, and discloses a circuit configuration thatsuppresses the occurrence of ripple-shaped noise in an output of asignal amplifier circuit by feedback means.

Furthermore, a technique described in Patent Document 6 relates to anamplifier circuit that compensates an offset, in which a feedbackcircuit is prepared for the purpose of offset cancellation, and thefeedback circuit herein is coupled to a signal node before the signalnode in which the hall electromotive force signal modulated by thechopper clock is demodulated by a demodulator.

Further, a technique described in Patent Document 7 relates to, forexample, a magnetic field sensor, which is provided with a sensorelement for outputting a sensor signal including an interfering signal,an evaluation apparatus coupled to this sensor element, and a subtractorfor subtracting the interfering signal from the sensor signal. Thetechnique also relates to an interfering signal compensation method ofthe sensor and discloses an example in which a ΔΣ AD converter is usedfor signal processing of a hall element.

Further, a technique described in Patent Document 8 relates to a currentmeasuring device for measuring a current flowing in the target object bymeans of measuring the magnetic field induced by the current flowing inthe target object, and discloses an example in which double integral ADconversion is used for signal processing of a hall element.

PRIOR ART DOCUMENT Patent Documents

-   Patent Document 1: JP 2008-309626 A-   Patent Document 2: JP 2011-163928 A-   Patent Document 3: JP 2011-169811 A-   Patent Document 4: JP 2010-507095 T-   Patent Document 5: U.S. Pat. No. 7,764,118 B2-   Patent Document 6: U.S. Pat. No. 6,674,322 B2-   Patent Document 7: JP 2007-525680 T-   Patent Document 8: JP 2004-069466 A

Non Patent Documents

-   Non Patent Document 1: Written by R S Popovic, Hall Effect Devices    (ISBN-10:0750300965) Inst of Physics Pub Inc (1991/05)-   Non Patent Document 2: IEEE Journal of Solid-State Circuits, Vol.    32, No. 6, 1997, Pages 829 to 836, Written by Bilotti et al.,    “Monolithic Magnetic Hall Sensor Using Dynamic Quadrature Offset    Cancellation”-   Non Patent Document 3: IEEE Journal of Solid-State Circuits, Vol.    41, No. 12, 2006, Pages 2729 to 2736, Written by Burt and Zhang, “A    Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch    Filter With Synchronous Integration Inside the Continuous-Time    Signal Path”-   Non Patent Document 4: IEEE Journal of Solid-State Circuits, Vol.    44, No. 12, 2009, Pages 3232 to 3243, Written by Wu et al., “A    Chopper Current-Feedback Instrumentation Amplifier With a 1 mHz 1/f    Noise Corner and an AC-Coupled Ripple Reduction Loop”-   Non Patent Document 5: IEEE Journal of Solid-State Circuits, Vol.    40, No. 7, 2005, Pages 1533 to 1540, Written by Motz et al., “A    Chopped Hall Sensor With Small Jitter and Programmable “True    Power-On” Function”

SUMMARY OF THE INVENTION Problem to be Solved

However, the techniques described in Patent Documents 1 to 3 do notdisclose anything about a difference calculation circuit for detecting,in the output voltage signals, a component synchronized with the chopperclock by performing sampling at a timing obtained from the chopperclock, as disclosed in the present invention.

Further, in the technique described in Patent Document 4, ripple-shapednoise of an offset voltage modulated by a chopper clock is reduced by afilter in a subsequent stage, but in this case, various problems canoccur as described below.

One use of the magnetic sensor using a hall element is a current sensor.In the current sensor using a hall element, an intensity of a magneticfield induced by a target current to be measured is measured in order tomeasure an amount of current flowing in a current conductor, which makesit possible to measure even a large current in a non-contact manner.Accordingly, the current sensor using a hall element is a sensor verysuitable for measurement of an inverter current of a motor, and thelike.

This current sensor is used to detect an inverter current which isswitched at a high frequency, and is generally required to have a fastresponse of 10 μ-seconds or less in terms of a signal processing delaytime, as well as a wide-band property of approximately 100 kHz.

In a case where the hall element is used for the current sensor, it isdifficult to achieve high accuracy in regard to detection accuracy ofthe current detection unless measures to cancel the offset voltages (theoffset voltage of the hall element and the offset voltage of the signalamplifier circuit) are taken. In view of this, in a case where the hallelement is used as the current sensor, the above-mentioned offsetcancellation method using a chopper clock is used.

In a case where the above-mentioned offset cancellation method is usedin the current sensor, if a narrow-band lowpass filter is used to reduceripple-shaped noise occurring in the output signal of the signalamplifier circuit, it becomes difficult to satisfy the above-mentionedrequirements such as the wide-band property and fast response. This isbecause the narrow-band lowpass filter has a long delay time (groupdelay time) of the filter. In addition, a problem with an increase innoise may be also caused.

On the other hand, a circuit configuration is also known in which afeedback is prepared from the output of the signal amplifier circuit tothe signal amplifier circuit so that ripples do not occur, instead ofreducing ripple-shaped noise occurring in the output signal of thesignal amplifier circuit by a filter in the subsequent stages. That is,the circuit configuration detects a DC offset that causes theripple-shaped noise from the ripple-shaped noise occurring in the outputsignal of the signal amplifier circuit, and the detected DC offset issubtracted in the signal amplifier circuit, so as to prevent theoccurrence of the ripple-shaped noise. An example of this circuitconfiguration is exemplified in Non Patent Document 4.

In the circuit configuration disclosed in Non Patent Document 4,capacitive coupling by use of capacitors is used so as to detect a DCoffset voltage component in the ripple-shaped noise occurring in theoutput signal of the signal amplifier circuit. However, theconfiguration using such capacitors cannot be used when a targetfrequency bandwidth to be detected is wide as in the case of the currentsensor.

In order to explain the reason thereof, the following describes a cleardistinction between the hall electromotive force signal detectioncircuit fora current sensor, used for current detection of an inverter,and the signal amplifier circuit used for an instrumentation (e.g., seeNon Patent Document 4).

In the case of the above-mentioned Non Patent Document 4 belonging to atechnical field of the signal amplifier circuit for instrumentation, thesignal amplifier circuit is designed for the purpose of detecting alow-frequency signal of a few Hz, and there is a sufficient differenceof approximately 10000 times between the frequency (40 kHz) of thechopper clock described in Non Patent Document 4 and a frequencybandwidth (a few Hz) of a target signal to be detected. In view of this,even if the DC offset voltage is detected in the ripple-shaped noise bymeans of capacitive coupling using capacitors, the detected DC offsetvoltage is not mixed with the target signal to be detected.

On the other hand, in the current sensor used for current detection ofan inverter, since a bandwidth of a target current signal to be detectedis wide (approximately 100 kHz), a frequency of the chopper clock shouldbe correspondingly increased to a higher-frequency side. However, due tolimitations in circuit design, such as settling of the output signal ofthe signal amplifier circuit, the frequency of the chopper clock in thecurrent sensor is around 500 kHz at most. As understood from this, inthe current sensor, the ratio between the frequency bandwidth of thetarget signal to be detected and the frequency of the chopper clock isonly around five times at most. Accordingly, when the DC offset voltageis detected in the ripple-shaped noise, the possibility of mixing thedetected DC offset voltage with the target signal to be detected willincrease. In view of this, in the current sensor used for currentdetection of an inverter, in order to detect the DC offset voltage fromripple-shaped noise, it is necessary to design a more accurate method,rather than a simple method such as capacitive coupling by use ofcapacitors as disclosed in Non Patent Document 4.

Further, the technique described in Patent Document 5 is disclosed as acontinuous-time analog switch which performs switching control of thepolarity of a differential signal between inversion and non-inversion,by use of a “third chopping circuit” which modifies the signal couplingof the differential signal. In contrast, the difference calculationcircuit of the present invention performs discrete time sampling of theinput signal to the difference calculation circuit, so as to calculatethe time variation of the input signal in a given period of time.

Further, in the technique described in Patent Document 6, “DEM1”indicates a chopper demodulator, however, this technique is differentfrom the configuration of the present invention in that feedback isperformed before “DEM1” as the chopper demodulator.

Differences between the present invention and Non Patent Document 5 andPatent Document 6 described above are investigated below. In Non PatentDocument 5 and Patent Document 6, a feedback circuit is prepared for thepurpose of offset cancellation. However, the feedback in Non PatentDocument 5 and Patent Document 6 is essentially different from that ofthe present invention in that the feedback is performed from a signalnode before the hall electromotive force signal modulated by a chopperclock is demodulated by a demodulator. Further, Patent Documents 7 and 8do not disclose anything about the characteristic configuration of thepresent invention at all.

Further, when the hall electromotive force signal detection circuit isused in an environment with high-frequency noise, such as for aninverter, the main signal path of the hall electromotive force signaldetection circuit is preferably a circuit that is able to performcontinuous-time signal processing, rather than discrete-time signalprocessing, in order to prevent fold over noise by discretization intime (sampling).

The present invention is accomplished in view of such circumstances, andan object of the present invention is to provide a hall electromotiveforce signal detection circuit and a current sensor thereof each ofwhich has excellent accuracy, wide band characteristics, and fastresponse and further has a main signal path of the circuit configurableby use of a continuous-time signal processing circuit.

Solution to the Problem

The present invention is accomplished in order to achieve the aboveobject. According to an aspect of the present invention, there isprovided a hall electromotive force signal detection circuit configuredto suppress an offset signal component in a signal composed of a hallelectromotive force signal generated in a Hall element and the offsetsignal component, and amplify the hall electromotive force signal togenerate an output signal, the hall electromotive force signal detectioncircuit including: a signal amplifier circuit configured to amplify anoutput of the hall element and output a signal having the offset signalcomponent modulated at a frequency of a chopper clock; a differencecalculation circuit configured to sample a component synchronous withthe chopper clock out of an output signal of the signal amplifiercircuit at a timing synchronous with the chopper clock, and output adifference between sampling results which are sampled at different time;an integrating circuit configured to integrate the output of thedifference calculation circuit in the time domain; and a feedbackcircuit configured to feed back an output signal of the integratingcircuit to the signal amplifier circuit.

Further, the hall electromotive force signal detection circuit includesa first switching circuit configured to perform switching operations onterminal pairs of the Hall element in which a terminal pair for drivinga driving current to the hall element and a terminal pair for detectingthe hall electromotive force signal are interchanged, and to modulatethe hall electromotive force signal generated in the hall element at thefrequency of the chopper clock. The signal amplifier circuit amplifiesthe output signal from the first switching circuit and the output signalof the signal amplifier is modulated at the frequency of the chopperclock, so that the hall electromotive force signal is demodulated to alow-frequency component including a direct current component, andoutputs a signal having the offset signal component modulated at thefrequency of the chopper clock.

Further, the signal amplifier circuit includes: a first transconductanceelement configured to convert an output voltage signal of the firstswitching circuit into a current so as to generate a first current;resistors configured to perform voltage-division on a component includedin the output voltage signal of the first switching circuit at apredetermined ratio; a second switching circuit configured to invert thepolarity of a voltage generated by the voltage-division according to thechopper clock; and a second transconductance element configured toconvert an output voltage from the second switching circuit into acurrent so as to generate a second current. The feedback circuitincludes a third transconductance element configured to convert anoutput voltage from the integrating circuit into a current so as togenerate a third current, and with regard to a current sum of the firstcurrent I1, the second current I2, and the third current I3, thefeedback circuit performs feedback operation in which a DC componentincluded in the sum of the first current and the second current in thesignal amplifier circuit is added with the third current such that thecurrent sum becomes zero (I1+I2+I3=0).

Further, a third switching circuit configured to modulate an inputsignal at the frequency of the chopper clock, and an output stagecoupled to the third switching circuit are provided in a subsequentstage of the first transconductance element.

Further, a fourth transconductance element is provided between asubsequent stage of the third switching circuit and the differencecalculation circuit.

Further, the difference calculation circuit and the integrating circuitare switched capacitor circuits.

Further, the difference calculation circuit is composed of ADconverters, and the integrating circuit is constituted of digitalcircuits.

Further, the AD converter is a ΔΣ-modulation AD converter.

Further, the AD converter is a double-integral AD converter.

Further, according to another aspect of the present invention, there isprovided a current sensor using the above-mentioned hall electromotiveforce signal detection circuit.

Advantageous Effects of the Invention

According to the present invention, it is possible to provide a hallelectromotive force signal detection circuit and a current sensorthereof each of which has excellent accuracy, wide band characteristics,and fast response and further has a main signal path of the circuit isconfigurable by a continuous-time signal processing circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate hall electromotive force detection at thetime when the direction of a driving current that biases a hall elementis switched between 0 degree and 90 degrees every time the phase of thechopper clock is changed between two values, i.e., φ1 and φ2.

FIGS. 2A to 2D illustrate signal waveforms occurring in the hallelement.

FIG. 3 illustrates a signal spectrum of a signal Vhall occurring in thehall element.

FIG. 4 is a circuit configuration diagram to describe a hallelectromotive force signal detection circuit as a premise of the presentembodiment.

FIG. 5 is a circuit configuration diagram to understand FIG. 4.

FIG. 6 illustrates a signal spectrum in an output voltage Vout of asignal amplifier circuit.

FIG. 7 is a circuit configuration diagram to describe one example of thehall electromotive force signal detection apparatus according to thepresent embodiment.

FIGS. 8A to 8C illustrate a state where Vout(φ1) and Vout(φ2) aredetected by sampling in a case where there is no time variation in atarget magnetic field to be detected by a magnetic sensor using a hallelement or the time variation is moderately slow.

FIGS. 9A to 9C illustrate waveforms of a signal amplifier circuit Voutin a case where the time variation is fast in a target magnetic field Bto be detected by the magnetic sensor using a hall element.

FIG. 10 is a circuit configuration diagram in which a differencecalculation circuit and an integrating circuit in the hall electromotiveforce signal detection circuit according to the present embodiment areimplemented with switched capacitor circuits.

FIG. 11 is a circuit configuration diagram in which the differencecalculation circuit and the integrating circuit in the hallelectromotive force signal detection circuit according to the presentembodiment are implemented with an AD converter, an integrator by use ofdigital circuit, and a DA converter.

FIG. 12 is a circuit configuration diagram illustrating an example ofthe difference calculation circuit in the hall electromotive forcesignal detection circuit according to the present embodiment, and anintegrating circuit including an ΔΣ-type AD converter and a DAconverter.

FIG. 13 is a circuit configuration diagram illustrating an example usinga double-integral AD converter, as the difference calculation circuit inthe hall electromotive force signal detection circuit according to thepresent embodiment, and an integrating circuit including a DA converter.

FIG. 14 illustrates the operation of the double-integral AD converter.

FIG. 15 is a circuit configuration diagram illustrating an example of afeedback circuit that is different from the feedback circuit of the hallelectromotive force signal detecting apparatus according to the presentembodiment as illustrated in FIG. 7.

DESCRIPTION OF EMBODIMENTS

With reference to drawings, the following describes embodiments of thepresent invention.

The above-mentioned description deals with offset cancellation techniqueby use of the driving method (the spinning current method) of a hallelement using a chopper clock. As to the hall element that performs thespinning current method, the following describes a configuration of ahall electromotive force signal detection circuit, which will be apremise of the present embodiment, with reference to FIG. 4.

FIG. 4 is a circuit configuration diagram to describe a hallelectromotive force signal detection circuit, as a premise of thepresent embodiment, and FIG. 5 is a circuit configuration diagram tounderstand FIG. 4. In these figures, a reference sign 1 indicates a hallelement, a reference sign 2 indicates a first switching circuit, areference sign 3 indicates a signal amplifier circuit, a reference sign4 indicates a chopper clock generation circuit, a reference sign 31indicates a first transconductance element (a transistor differentialpair; Gm, 1), a reference sign 32 indicates a second switching circuit,a reference sign 33 indicates a second transconductance element (atransistor differential pair; Gm, 2), a reference sign 34 indicates athird switching circuit, a reference sign 35 indicates an output stageof the signal amplifier circuit 3 (a transistor differential pair; Gm,out), and a reference sign 36 indicates an operational amplifier.

In the hall electromotive force signal detection circuit illustrated inFIG. 4, a signal Vhall input into the signal amplifier circuit 2 fromthe hall element 1 is input to the transistor differential pair Gm, 1,and a current I1 is generated according to Expression 2. Here, therealso exist an offset Vos (Gm, 1) in the transistor differential pair Gm,1 of the signal amplifier circuit, and therefore, the current I1 isaffected by this offset voltage Vos(Gm, 1).

Note that, in FIG. 4, the current I1 is a differential signal. In viewof this, in regard to reference signs I1+ and I1− in FIG. 4, thefollowing relationship is assumed: I1=(I1+)−(I1−).

$\begin{matrix}\left\lbrack {{Math}.\mspace{14mu} 2} \right\rbrack & \; \\{{{Output}\mspace{14mu} {Current}\mspace{14mu} I\; 1\mspace{14mu} {from}\mspace{14mu} {Transistor}\mspace{14mu} {Differential}\mspace{14mu} {Pair}\mspace{14mu} {Gm}},{1\left\{ \begin{matrix}\begin{matrix}{{{r\; 1({\varphi 1})} = {Gm}},{{1 \cdot \left( {{{Vhall}({\varphi 1})} + {{Vos}\left( {{Gm},1} \right)}} \right)} =}} \\{{Gm},{1 \cdot \left( {{+ {{Vsig}(B)}} + {{Vos}({Hall})} + {{Vos}\left( {{Gm},1} \right)}} \right)}}\end{matrix} & \left( {{{Chopper}\mspace{14mu} {Clock}} = {\varphi 1}} \right) \\\begin{matrix}{{{r\; 1({\varphi 2})} = {Gm}},{{1 \cdot \left( {{{Vhall}({\varphi 2})} + {{Vos}\left( {{Gm},1} \right)}} \right)} =}} \\{{Gm},{1 \cdot \left( {{- {{Vsig}(B)}} + {{Vos}({Hall})} + {{Vos}\left( {{Gm},1} \right)}} \right)}}\end{matrix} & \left( {{{Chopper}\mspace{14mu} {Clock}} = {\varphi 2}} \right)\end{matrix} \right.}} & {{Expression}\mspace{14mu} 2}\end{matrix}$

Note that in the hall electromotive force signal detection circuitillustrated in FIG. 4, the number of hall elements 1 is one. However,since a hall electromotive force signal generated in the hall element 1is converted into a current according to Expression 2, even in the casewhere a plurality of hall elements is used, it is possible to detect thesum of the hall electromotive force signals generated in the pluralityof hall elements by converting hall electromotive force signalscorresponding to respective hall elements into currents and adding thosecurrents together.

In the hall electromotive force signal detection circuit illustrated inFIG. 4, a feedback from the output voltage Vout by use of resistors R1and R2 is prepared, and a feedback voltage Vfb from the output voltageVout is generated according to Expression 3.

$\begin{matrix}\left\lbrack {{Math}.\mspace{14mu} 3} \right\rbrack & \; \\{{{Feedback}\mspace{14mu} {from}\mspace{14mu} {Output}\mspace{14mu} {Voltage}\mspace{14mu} {Vout}\mspace{14mu} {of}\mspace{14mu} {Signal}\mspace{14mu} {Amplifier}\mspace{14mu} {Circuit}\mspace{14mu} {Vfb}} = {\frac{R\; 1}{{R\; 1} + {R\; 2}}{Vout}}} & {{Expression}\mspace{14mu} 3}\end{matrix}$

The transistor differential pair Gm, 2 in the signal amplifier circuit 3is driven by the feedback voltage Vfb represented by Expression 3 fromthe output voltage Vout. However, since there exists an offset Vos(Gm,2) in the transistor differential pair Gm, 2, a current I2 output fromGm, 2 is represented by Expression 4.

Note that, in FIG. 4, the current I2 is a differential signal. In viewof this, in regard to reference signs I2+ and I2− in FIG. 4, thefollowing relationship is assumed: I2=(I2+)−(I2−).

$\begin{matrix}\left\lbrack {{Math}.\mspace{14mu} 4} \right\rbrack & \; \\{{{{Output}\mspace{14mu} {Current}\mspace{14mu} I\; 2\mspace{14mu} {from}\mspace{14mu} {Transistor}\mspace{14mu} {Differential}\mspace{14mu} {Pair}\mspace{14mu} {Gm}},2}\left\{ \begin{matrix}{{{I\; 2({\varphi 1})} = {+ {Gm}}},{{2 \cdot {Vfb}} + {Gm}},{2 \cdot {{Vos}\left( {{Gm},2} \right)}}} & \left( {{{Chopper}\mspace{14mu} {Clock}} = {\varphi 1}} \right) \\{{{I\; 2({\varphi 2})} = {- {Gm}}},{{2 \cdot {Vfb}} + {Gm}},{2 \cdot {{Vos}\left( {{Gm},2} \right)}}} & \left( {{{Chopper}\mspace{14mu} {Clock}} = {\varphi 2}} \right)\end{matrix} \right.} & {{Expression}\mspace{14mu} 4}\end{matrix}$

In the hall electromotive force signal detection circuit illustrated inFIG. 4, the feedback works so that the sum of the output current I1 fromthe transistor differential pair Gm, 1 and the output current I2 fromthe transistor differential pair Gm, 2 becomes zero. Accordingly, whenthe output voltage Vout of the hall electromotive force signal detectioncircuit of FIG. 4 is calculated on the basis of I1+I2=0, Expression 5 isobtained.

Here, as represented by Expression 5, it should be noted that the signalVsig(B) which is modulated by the chopper clock of the chopper clockgeneration circuit 4 is demodulated by the third switching circuit 34 inFIG. 4. As such, the signal Vsig (B) to be detected is modulated by thechopper clock in the previous stage, and then demodulated by the chopperclock in the subsequent stage. In view of this, the category of thecircuit which includes the signal amplifier circuit 3 of FIG. 4 iscalled chopper amplifier.

$\begin{matrix}\left\lbrack {{Math}.\mspace{14mu} 5} \right\rbrack & \; \\{{{Output}\mspace{14mu} {Voltage}\mspace{14mu} {Vout}\mspace{14mu} {of}\mspace{14mu} {Hall}\mspace{14mu} {Electromotive}\mspace{14mu} {Force}\mspace{14mu} {Signal}\mspace{14mu} {Detection}\mspace{14mu} {Circuit}}\left\{ \begin{matrix}{{{Vout}({\varphi 1})} = \begin{matrix}{{\left( {1 + \frac{R\; 2}{R\; 1}} \right)\left( \frac{{Gm},1}{{Gm},2} \right){{Vsig}(B)}} -} \\\left\{ \frac{{Gm},{{{1 \cdot {Vos}}({Hall})} + {Gm}},{{1 \cdot {{Vos}\left( {{Gm},1} \right)}} + {Gm}},{2 \cdot {{Vos}\left( {{Gm},2} \right)}}}{{Gm},2} \right\}\end{matrix}} & \left( {{{Chopper}\mspace{14mu} {Clock}} = {\varphi 1}} \right) \\{{{Vout}({\varphi 2})} = \begin{matrix}{{\left( {1 + \frac{R\; 2}{R\; 1}} \right)\left( \frac{{Gm},1}{{Gm},2} \right){{Vsig}(B)}} +} \\\left\{ \frac{{Gm},{{1 \cdot {{Vos}({Hall})}} + {Gm}},{{1 \cdot {{Vos}\left( {{GM},1} \right)}} + {Gm}},{2 \cdot {{Vos}\left( {{Gm},2} \right)}}}{{Gm},2} \right\}\end{matrix}} & \left( {{{Chopper}\mspace{14mu} {Clock}} = {\varphi 2}} \right)\end{matrix} \right.} & {{Expression}\mspace{14mu} 5}\end{matrix}$

The polarity of the part which is placed between parentheses “{” and “}”in Expression 5 is inverted every time the phase of the chopper clock isswitched between φ1 and φ2. As can be seen from this, in the hallelectromotive force signal detection circuit illustrated in FIG. 4,every time the phase of the chopper clock is switched between φ1 and φ2,the sum of the offset voltage of the hall element, the offset voltage ofGm, 1 and the offset voltage of Gm, 2 is modulated by the chopper clock,and ripple-shaped noise in the output Vout of the signal amplifiercircuit is generated. From Expression 5, it can be understood that thesignal spectrum of the output Vout of the signal amplifier circuitexhibits a spectrum as illustrated in FIG. 6. In FIG. 6, the componentlocated in the chopper clock frequency f_chop is ripple-shaped noisesuperposed on the output signal Vout of the signal amplifier circuit.

Further, in a case where presence of the above-mentioned ripple-shapednoise is removed from Expression 5, Expression 6 is obtained. It isshown that, in the hall electromotive force signal detection circuitillustrated in FIG. 4, the hall electromotive force signal Vsig(B)corresponding to a target magnetic field B to be detected by themagnetic sensor is amplified by the predetermined signal amplificationgain (1+R2/R1) (Gm, 1/Gm, 2).

$\begin{matrix}\left\lbrack {{M{ath}}.\mspace{14mu} 6} \right\rbrack & \; \\{{{Expression}\mspace{14mu} {of}\mspace{14mu} {Signal}\mspace{14mu} {Amplification}\mspace{14mu} {of}\mspace{14mu} {Hall}\mspace{14mu} {Electromotive}\mspace{14mu} {Force}\mspace{14mu} {Signal}\mspace{14mu} {Vout}} = {\left( {1 + \frac{R\; 2}{R\; 1}} \right)\left( \frac{{Gm},1}{{Gm},2} \right){{Vsig}(B)}}} & {{Expression}\mspace{14mu} 6}\end{matrix}$

With reference to drawings, the following describes embodiments of thepresent invention.

FIG. 7 is a circuit configuration diagram to describe one example of thehall electromotive force signal detection circuit according to thepresent embodiment. In the figure, a reference sign 11 indicates a hallelement, a reference sign 12 indicates a first switching circuit, areference sign 13 indicates a signal amplifier circuit, a reference sign14 indicates a chopper clock generation circuit, a reference sign 15indicates a difference calculation circuit, a reference sign 16indicates an integrating circuit, a reference sign 17 indicates a thirdtransconductance element (a transistor differential pair; Gm, 3), areference sign 131 indicates a first transconductance element (atransistor differential pair; Gm, 1), a reference sign 132 indicates asecond switching circuit, a reference sign 133 indicates a secondtransconductance element (a transistor differential pair; Gm, 2), areference sign 134 indicates a third switching circuit, and a referencesign 135 indicates an output stage of the signal amplifier circuit 13 (atransistor differential pair; Gm, out). Note that the first switchingcircuit 12 is a switching circuit which is prepared to implement thespinning current method. Further, the portion (a circuit including “athird transconductance element 17”) which receives an output of theintegrating circuit 16 and returns it to the signal amplifier circuit 13is called feedback circuit.

The present embodiment is a hall electromotive force signal detectioncircuit for generating an output voltage signal obtained by amplifying ahall electromotive force signal generated in a hall element, with apredetermined signal amplification gain. The first switching circuit 12is configured to perform switching operations on the terminal pairs ofthe hall element 11 in which a terminal pair for driving a drivingcurrent to the hall element 11 and a terminal pair for detecting a hallelectromotive force signal are interchanged, and to modulate a hallelectromotive force signal generated in the hall element 11 at thefrequency of the chopper clock.

Further, the chopper clock generation circuit 14 generates a chopperclock for periodically driving the first switching circuit 12. Further,the signal amplifier circuit 13 amplifies an output voltage signal fromthe first switching circuit 12.

Further, the difference calculation circuit 15 samples a signalcomponent synchronized with the chopper clock generated by the chopperclock generation circuit 14, out of the output voltage signal of thesignal amplifier circuit 13, at a timing obtained from the chopperclock, so as to detect the signal component. Further, the integratingcircuit 16 integrates an output of the difference calculation circuit 15in the time domain. Further, the third transconductance element 17converts an output voltage of the integrating circuit 16 into a currentto generate a third current.

Further, the signal amplifier circuit 13 includes: the firsttransconductance element 131 for converting a hall electromotive forcesignal into a current so as to generate a first current; resistors R1and R2 for performing voltage-division on the output voltage signal at agiven ratio; the second switching circuit 132 for reversing a polarityof a voltage generated by the voltage-division, according to the chopperclock; the second transconductance element 133 for converting an outputvoltage of the second switching circuit 132 into a current so as togenerate a second current; the third switching circuit 134 provided inthe subsequent stage of the first transconductance element 131 andperforming a demodulation operation at a chopper clock frequency; andthe output stage 135 coupled to this third switching circuit 134.

With such a configuration, an output voltage signal from the integratingcircuit 16 is fed back to the signal amplifier circuit 13 via the thirdtransconductance element 17. That is, with regard to a current sum ofthe first current I1, the second current I2, and the third current I3,feedback is performed on a DC component included in a sum of the firstcurrent and the second current via the third transconductance element 17which converts an output voltage from the integrating circuit 16 into acurrent to generate the third current, so that the sum including thethird current becomes zero (I1+I2+I3=0).

Further, in the present embodiment, a current sensor may be constitutedof the above-mentioned hall electromotive force signal detectioncircuit.

(Feedback Circuit for Suppressing Occurrence of Ripple)

The following describes the hall electromotive force signal detectioncircuit according to the present embodiment with reference to FIG. 7. InFIG. 7, between the output signal Vout of the signal amplifier circuit13 which amplifies a hall electromotive force signal and the circuitnode in which the current I1 and the current I2 are added in the signalamplifier circuit 13, a feedback circuit is prepared.

This feedback circuit is constituted of the difference calculationcircuit 15, the integrating circuit 16, and the third transconductanceelement 17. The current I3 output from this third transconductanceelement 17 acts to cancel a component Ios of a DC offset currentincluded in a current I1+I2=Gm, 1·Vhall+Gm, 2·Vfb, represented byExpression 7.

Note that, in FIG. 7, the current I3 is a differential signal. In viewof this, in regard to reference signs I3+ and I3− in FIG. 7, thefollowing relationship is assumed: I3=(I3+)−(I3−).

Expression 7: DC Offset Current Ios Causing Ripple-Shaped Noise

Ios=Gm,1·Vos(Hall)+Gm,1·Vos(Gm,1)+Gm,2·Vos(Gm,2)  [Math. 7]

The DC offset current Ios, represented by Expression 7, is a DC offsetcurrent resulted from the voltage to current conversion in which anoffset voltage of the hall element, offset voltages in the transistordifferential pair (Gm, 1) 131, and the transistor differential pair (Gm,2) 133 are converted to an current signal by use of the transistordifferential pair. When this DC offset current Ios is modulated at afrequency of a chopper clock in the third switching circuit 134,ripple-shaped noise (FIG. 9) occurs in the output voltage signal Vout ofthe signal amplifier circuit 13. In view of this, when feedback isperformed by the feedback current I3 so that the DC component Ioscontained in (I1+I2) is added with I3 and the resulting sum becomeszero, it is possible to eliminate the occurrence of the ripple-shapednoise.

(Difference Calculation Circuit)

For the purpose of detecting a component of a chopper clock frequencyfrom the ripple-shaped noise in the signal amplifier output signal Voutwith high accuracy, the above-mentioned feedback performs timediscretization (sampling) on the signal amplifier output signal Vout ata timing just before the chopper clock changes.

That is, Vout(φ1) is detected by sampling at a timing just before achopper clock phase changes from φ1 to φ2, Vout (φ2) is detected bysampling at a timing just before the chopper clock phase changes from φ2to φ1, and a difference signal Vout (φ1)-Vout (φ2) between Vout (φ1) andVout (φ2) is calculated as a discrete-time signal. Thus, it is thefunction of the difference calculation circuit 15 in the presentembodiment to perform a calculation of the time variation of Voutbetween two timing separated at a certain time period (calculationcorresponding to time derivatives).

(Integrating Circuit in Subsequent Stage of Difference CalculationCircuit)

In the example in FIG. 7 of the hall electromotive force signaldetecting apparatus of the present embodiment, the integrating circuit16 is placed in a subsequent stage of the difference calculation circuit15. This integrating circuit 16 performs time integration (lowpassfilter) on an amplitude component of the ripple-shaped noise detected bythe difference calculation circuit 15, i.e., a DC component which is thesource of the ripple-shaped noise, to remove various noise componentsfrom an output signal from the difference calculation circuit 15.

As described later, in the hall electromotive force signal detectingapparatus of the present embodiment, since the difference calculationcircuit 15 is a circuit for performing time discretization (sampling), aswitched capacitor circuit and a digital circuit can be used for theintegrating circuit 16, and, as a result, various desirable features canbe realized.

(Hall Electromotive Force Signal Detection Circuit according to PresentEmbodiment)

As for the circuit configurations which suppress the occurrence ofripple-shaped noise in the output of the signal amplifier circuit 13 byfeedback means, these circuit configurations are described in Non PatentDocument 4 and Patent Document 5 which are mentioned before. Although,each of these documents deals with a circuit of capacitive couplingusing capacitors and a circuit to invert its signal polarity with switchcircuit as a circuit measure for detecting a DC component in theripple-shaped noise, there is no description in these documents aboutthe concept of a difference calculation circuit which is acharacteristic configuration of the present embodiment.

It is explained in the following that the difference calculationcircuit, which is the characteristic configuration of the presentembodiment, makes it possible to achieve high accuracy of feedback thatsuppresses the occurrence of ripple-shaped noise in an output of asignal amplifier circuit. Particularly, the difference calculationcircuit 15, which is the characteristic configuration of the presentembodiment, can be a suitable circuit configuration in the applicationssuch as current sensor designed to detect a switching current of aninverter, where a frequency bandwidth of a target magnetic field signalto be detected is relatively wider than the chopper clock frequency.

FIGS. 8A to 8C illustrate a state where Vout (φ1) and Vout (φ2) aredetected by sampling in a case where there is no time variation in thetarget magnetic field to be detected by a magnetic sensor using a hallelement or the time variation is slow enough. Even in this case, if aslew rate of an output stage (Gm, out) 135 of the signal amplifier forthe rising voltage is unbalanced with a slew rate thereof for thefalling voltage, an unbalance arises in the waveform of theripple-shaped noise between the rising period and the falling period.

Under these circumstances, in the case of Non Patent Document 4 andPatent Document 5, the unbalance between the period of rising voltageand the period of falling voltage in the ripple-shaped noise causes anerror in feedback to suppress the occurrence of the ripple-shaped noise.As the chopper clock frequency is increased to a higher frequency, suchunbalance becomes more significant.

In contrast to this, in the difference calculation circuit, which is thecharacteristic configuration of the present embodiment, sampling isperformed at a timing just before the chopper clock changes. In view ofthis, as far as the ripple-shaped noise settles into a constant valuewithin the half of the chopper clock period, the difference calculationcircuit is not affected by such unbalance between the rising period andthe falling period.

FIGS. 9A to 9C illustrate waveforms of the signal amplifier circuit Voutin a case where time variation is fast in the target magnetic field B tobe detected by the magnetic sensor using a hall element. The situationillustrated in FIGS. 9A to 9C occurs when the band width of the signalfrequency of the target magnetic field B to be detected is relativelywider than the chopper clock frequency, as in the case of a currentsensor designed to detect a switching current of an inverter.

In such a case, a signal Vsig(B) corresponding to the time variation ofthe target magnetic field B to be detected is mixed into sampled Vout(φ1) and Vout (φ2) (Expression 8). Notwithstanding, the circuitconfiguration of the hall electromotive force signal detection circuitaccording to the present embodiment is a circuit configuration which canminimize the influence of Vsig (B).

In order to describe this feature of the present embodiment, thefollowing deals with a case where a value of Vout(φ1) sampled in chopperclock phase φ1 at a time n is represented to be Vout (φ1) (n),similarly, a value of Vout (φ2) sampled in chopper clock phase φ2 at atime n is represented to be Vout(φ2) (n), and a difference signalVout(φ1) (n)−Vout(φ2) (n) therebetween is integrated for N times withrespect to the time n. Here, in a case where the target magnetic field Bto be detected is a magnetic field induced by an inverter current thatdrives a motor, the signal Vsig(B) exhibits a sinusoidal wave form ofwhich cycle is the same as the cycle of the inverter driving current ofthe motor. Accordingly, if an integration times N herein is set to be asufficiently large number, it becomes possible to detect a ripplecomponent (a DC offset component as a source of ripple) with highaccuracy while eliminating the influence of Vsig (B), as understood fromExpression 9.

Further, it is a well-known fact that switched capacitor circuits anddigital circuits are suitable circuit configurations for the purpose ofrealizing integrating circuits and narrow-band filters.

$\begin{matrix}\left\lbrack {{Math}.\mspace{14mu} 8} \right\rbrack & \; \\{{{{Ripple}\mspace{14mu} {Detection}\mspace{14mu} {When}\mspace{14mu} {Time}\mspace{14mu} {Variation}\mspace{14mu} {of}\mspace{14mu} {Target}\mspace{14mu} {Magnetic}\mspace{14mu} {Signal}\mspace{14mu} B\mspace{14mu} {to}\mspace{14mu} {be}\mspace{14mu} {Detected}\mspace{14mu} {is}\mspace{14mu} {Fast}\mspace{14mu} {{Vout}({\varphi 1})}} - {{Vout}({\varphi 1})}} = {\left\{ {{Ripple}\mspace{14mu} {Component}} \right) + {{Vsig}(B)}}} & {{Expression}\mspace{14mu} 8} \\\left\lbrack {{Math}.\mspace{14mu} 9} \right\rbrack & \; \\{{{Elimination}\mspace{14mu} {of}\mspace{14mu} {Influence}\mspace{14mu} {of}\mspace{14mu} {{Vsig}(B)}\mspace{14mu} {on}\mspace{14mu} {Ripple}\mspace{14mu} {by}\mspace{14mu} {Integration}\mspace{14mu} {of}\mspace{14mu} \left\{ {{{Vout}({\varphi 1})} - {{Vout}({\varphi 2})}} \right\} {\sum\limits_{n = 1}^{N}\; \left\{ {{{{Vout}({\varphi 1})}(n)} - {{{Vout}({\varphi 1})}(n)}} \right\}}} = {{Nx}\left\{ {{Ripple}\mspace{14mu} {Component}} \right\}}} & {{Expression}\mspace{14mu} 9}\end{matrix}$

The difference calculation circuit, which is the characteristicconfiguration of the present embodiment, has the following twoadvantages because digital circuits can be utilized in the subsequentstages of the difference calculation circuit.

The first advantage when the digital circuit is used for the circuitplaced in the subsequent stage of the difference calculation circuit 15is the reduction of an initial pull-in time of the feedback loop thatsuppresses the occurrence of ripple-shaped noise in the output of thesignal amplifier circuit 13. As described above, this feedback loop is afeedback loop with a very narrow bandwidth, and therefore, a long timeis generally required for the initial pull-in time, where the initialpull-in time means the time which is required for the feedback loop toconverge and settle the ripple-shaped noise converged to zero after theinitial operation of the hall electromotive force signal detectioncircuit is started after power-on. Here, if a digital circuit is usedfor the circuit in the subsequent stage of the difference calculationcircuit 15, it is easy to implement, in the digital circuit, an adaptivealgorithm in which the time constant of the feedback loop may beswitched between the initial period before the initial pull-in operationis completed and the steady operation period after the initial pull-inoperation is completed, thereby making it possible to realize thereduction of the initial pull-in time.

The second advantage obtained when a digital circuit is used for thecircuit placed in the subsequent stage of the difference calculationcircuit 15 is the realization of robustness of the feedback loop. Thecurrent sensor used for detecting a switching current of an inverter isused under an environment with strong disturbance noise such aselectromagnetic induction noise and electrostatic induction noise whichare generated at the time of the switching of the inverter. Because ofthis, in the current sensor used for detecting a switching current of aninverter, the disturbance noise is input into the feedback loop thatsuppresses the occurrence of ripple-shaped noise in the output of thesignal amplifier circuit 13. However, in a case where a digital circuitis used for the circuit in the subsequent stage of the differencecalculation circuit, it is possible to implement algorithms that areinsusceptible to such disturbance noise in the digital circuit, therebymaking it possible to realize the robustness of the feedback loop.

(Example of Difference Calculation Circuit and Integrating Circuit usingSwitched Capacitor Circuits)

FIG. 10 is a circuit configuration diagram in which the differencecalculation circuit and the integrating circuit in the hallelectromotive force signal detection circuit according to the presentembodiment are implemented with switched capacitor circuits. Thedifference calculation circuit 15 is constituted of an operationalamplifier 15 a, capacitors C1, diff and C2, diff, and a switch, andcalculates a voltage difference between Vout(φ1) and Vout(φ2) to besampled sequentially in the capacitor C1, diff at an input side, so asto output Vdiff (see Expression 10).

Further, the integrating circuit 16 is constituted of an operationalamplifier 16 a, capacitors C1, int and C2, int, and a switch. Vint iscalculated by converting Vdiff sampled in the capacitor C1, int at theinput side into a charge (C1, int*Vdiff) and transferring the charge tothe capacitor C2, int to perform integral calculation (see Expression11).

Note that the difference calculation circuit 15 and the integratingcircuit 16 are switched capacitor circuits.

The difference calculation circuit 15, which is the characteristicconfiguration of the present embodiment, has a circuit configurationknown as Peak-To-Peak circuit, and calculates Vdiff=(C1, diff/C2,diff)×(1 Vout(φ1)−Vout(φ2)) according to the transfer function Hdiff(z)of the difference calculation circuit, as represented by Expression 10.

Herein, Peak-To-Peak circuit is taken as an example of the differencecalculation circuit to make explanation, but there are variousconfigurations of the difference calculation circuits usable herein, aswell as the Peak-To-Peak circuit.

$\begin{matrix}\left\lbrack {{Math}.\mspace{14mu} 10} \right\rbrack & \; \\{{{Transfer}\mspace{14mu} {Function}\mspace{14mu} {of}\mspace{14mu} {Time}\mspace{14mu} {Discretization}\mspace{14mu} {Differential}\mspace{14mu} {Circuit}\mspace{14mu} {Constituted}\mspace{14mu} {of}\mspace{14mu} {Swiched}\mspace{14mu} {Capacitor}\mspace{14mu} {Circuits}\mspace{14mu} {{Hdiff}(z)}} = {\left( \frac{{C\; 1},{diff}}{{C\; 2},{diff}} \right)\left( {1 - z^{- 1}} \right)}} & {{Expression}\mspace{14mu} 10}\end{matrix}$

The output signal Vdiff of the difference calculation circuit 15 in FIG.10 is integrated by the integrating circuit 16 constituted of theswitched capacitor circuits, to obtain voltage signal Vint. In theexample of the circuit configuration as illustrated in FIG. 10, thetransfer function Hint(z) of the integrating circuit is represented byExpression 11.

$\begin{matrix}\left\lbrack {{Math}.\mspace{14mu} 11} \right\rbrack & \; \\{{Transfer}\mspace{14mu} {Function}\mspace{14mu} {of}\mspace{14mu} {Integrating}\mspace{14mu} {circuit}\mspace{14mu} {Constituted}\mspace{14mu} {of}\mspace{14mu} {Switched}\mspace{14mu} {Capacitor}\mspace{14mu} {Circuits}\mspace{14mu} H\; {{int}(z)}\left( \frac{{C\; 1},{int}}{{C\; 2},{int}} \right)\left( \frac{z^{- 1}}{1 - z^{- 1}} \right)} & {{Expression}\mspace{14mu} 11}\end{matrix}$

(Circuit Configuration Using AD Converter, Integrator by DigitalCircuit, and DA converter)

FIG. 11 is a circuit configuration diagram in which the differencecalculation circuit and the integrating circuit in the hallelectromotive force signal detection circuit according to the presentembodiment are implemented with an AD converter, an integrator by use ofdigital circuits, and a DA converter. In the figure, a reference sign136 indicates an M-bit AD converter, a reference sign 138 indicates a DAconverter, a reference sign 138 a indicates an N-bit register, and areference sign 138 b indicates an N-bit DA converter.

A difference calculation circuit 15D is the M-bit AD converter 136, anintegrating circuit 16D is constituted of a digital integrator 137, andthe DA converter 138 constituted of the N-bit register 138 a and theN-bit DA converter 138 b.

According to the circuit configuration herein, the differencecalculation circuit 15D in the feedback circuit according to the presentembodiment is implemented with the AD converter 136, the integratingcircuit 16D therein is implemented with a digital circuit constituted ofthe digital integrator 137 and the DA converter 138, and the outputsignal of the integrating circuit 16D is converted into an analog signalVint by use of the DA converter 138 b. That is, the differencecalculation circuit 15D is constituted of the AD converter 136, theintegrating circuit 16D is constituted as the digital circuits 137 and138, and the voltage fed back to the third transistor differential pair(Gm, 3) 17 is generated by the DA converter 138 b.

(Example Using Difference Calculation Circuit Illustrated in FIG. 10 andIntegrating Circuit Including ΔΣ-Modulation AD Converter and DAConverter)

FIG. 12 is a circuit configuration diagram illustrating an example usingthe difference calculation circuit in the hall electromotive forcesignal detection circuit according to the present embodiment, and anintegrating circuit including a ΔΣ-type AD converter and a DA converter.A difference calculation circuit 150 has the same circuit configurationas the difference calculation circuit 15 illustrated in FIG. 10. Notethat a reference sign 150 a indicates an operational amplifier. Further,an integrating circuit 160 is constituted of an ΔΣ-modulation ADconverter 140 and an integrating circuit 16D as illustrated in FIG. 11,the integrating circuit 16D is constituted of a digital integrator 137and a DA converter 138. The ΔΣ-modulation AD converter 140 isconstituted of an integrating circuit 16 as illustrated in FIG. 10, acomparator 142 coupled to an operational amplifier 141 of thisintegrating circuit 16, a digital decimation filter 143 coupled to thiscomparator 142, and a one-bit DA converter 144 for feeding back theoutput of the comparator 142 to the operational amplifier 141constituting the integrating circuit.

In FIG. 12, similarly to the exemplary circuit configuration of FIG. 10,the operation of time-derivative is performed to get an analog signalVdiff by the difference calculation circuit (Peak-To-Peak circuit)implemented with switched capacitor circuit on Vout which is the outputof the signal amplifier 13. The integrating circuit into which theanalog signal Vdiff is input performs AD conversion of the signal Vdiffat an input stage of the integrating circuit, so as to perform integralcalculation by digital signal processing.

In FIG. 12, 1st order ΔΣ modulator 140 is used as an AD converter forperforming AD conversion of the analog signal Vdiff. A signal that isone-bit quantized by the comparator 142 in this ΔΣ modulator 140 isprocessed by the decimation filter 143 implemented as digital filter,and the digital signal ADC (Vdiff) of signed M-bit width is obtained asthe digitized signal Vdiff. This signed M-bit signal is integrated bythe digital-circuit integrator 137, and thus a signal of signed N-bitwidth is obtained. This signed N-bit signal is stored in the register138 a, and an analog voltage Vint is obtained by use of the N-bit DAconverter 138 b.

As illustrated in FIG. 12, if an appropriate AD converter and anappropriate DA converter are used, it is possible to constitute thefeedback circuit of the present embodiment so as to include digitalcircuits.

In the feedback circuit of the present embodiment, it is necessary tokeep track of the time variation of the offset voltage of the hallelement and the offset voltages of the transistor differential pairs.However, the time variation of the offset voltages that should betracked herein is very slow, and therefore, an AD converter with ahigh-speed operation is not required for the AD converter. Consequently,as in the case of the exemplary 1st order ΔΣ modulator illustrated inFIG. 12, it is possible to use a low-order ΔΣ modulator with a smallcircuit scale.

(Example Using Difference Calculation Circuit Including Double-IntegralAD Converter Including Integrating Circuit Illustrated in FIG. 10 andIntegrating Circuit Including DA Converter)

As described above, the feedback loop that suppresses the occurrence ofripples is intended to cancel a DC offset, and therefore becomes a loopwith extremely narrow bandwidth. In view of this, it is also possible touse an AD converter known as double-integral type, as the AD converter.The double-integral AD converter is a type that is generally used inlow-speed and high-accuracy measurement such as digital multimeter, andin the present embodiment, it is one of extremely preferable types of ADconversion as a type of the AD converter constituting theabove-mentioned feedback.

FIG. 13 is a circuit configuration diagram illustrating an example ofthe hall electromotive force signal detection circuit according to thepresent embodiment by use of an difference calculation circuitconstituted of a double-integral AD converter and a DA converter. In thefigure, a reference sign 151 indicates a double-integral AD converter, areference sign 151 a indicates an operational amplifier, a referencesign 151 b indicates an integration reset switch, a reference sign 151 cindicates a comparator, a reference sign 151 d indicates a controlcircuit, and a reference sign 151 e indicates a counter.

The double-integral AD converter 151 has the circuit configurationincluding the difference calculation circuit 15 shown in FIG. 10, and isconstituted of the comparator 151 c coupled to the operational amplifier151 a, the control circuit 151 d coupled to the comparator 151 c, andthe counter 151 e coupled to the control circuit 151 d. Further, anintegrating circuit 16D has a circuit configuration similar to theintegrating circuit illustrated in FIG. 11, and is constituted of adigital integrator 137 and a DA converter 138. The DA converter 138 isconstituted of an N-bit register 138 a and an N-bit DA converter 138 bcoupled to this N-bit register 138 a.

In FIG. 13, since it is possible to integrate a difference signalbetween Vout(φ1) and Vout(φ2), a differential operation is performed inan AD conversion operation by use of the double-integral AD converter,obtaining ADC (Vdiff) as a digitized signal.

An AD conversion operation of the double-integral AD converter 151 willbe described below, with reference to FIG. 14. After AD conversion isstarted, the integration reset switch 151 b is released in theintegrator, so as to integrate Vout(φ1)-Vout(φ2) for predetermined N1times. Then, an input selector switch control signal changes an inputvoltage to the integrator to +Vadc or to −Vadc according to the polarityof the output voltage of the operational amplifier 151 a of theintegrator, the output voltage being detected by the comparator 151 c.And the integration operation of the integrator is started again. Here,the polarity of the output voltage of the integrator is monitored by thecomparator 151 c, and integration is performed for N2 times so that theoutput voltage of the integrator becomes zero. The number of counts N2of the counter 151 e obtained through the control circuit 151 d is theAD conversion result of the double integral technique. That is, ADC(Vdiff)=N2 is obtained. The transfer function of the AD conversion usingthis double-integral AD converter 151 is represented by Expression 12where Vout (φ1) and Vout (φ2) sampled at an i time are assumed Vout (φ1)(i) and Vout (φ2) (i), respectively.

$\begin{matrix}\left\lbrack {{Math}.\mspace{14mu} 12} \right\rbrack & \; \\{{{{AD}\mspace{14mu} {Conversion}\mspace{14mu} {by}\mspace{14mu} {Double}} - {{integral}\mspace{14mu} {AD}\mspace{14mu} {Converter}\mspace{14mu} {\sum\limits_{i = 1}^{N\; 1}\; \left\{ {{{{Vout}({\varphi 1})}(i)} - {{{Vout}({\varphi 2})}(i)}} \right\}}}} = {N\; 2 \times \left( {\pm {Vadc}} \right)}} & {{Expression}\mspace{14mu} 12}\end{matrix}$

The AD conversion result N2 obtained by the double-integral AD converter151 is the result obtained by performing AD conversion on Vout (φ1)−Vout(φ2). This digital signal N2 is integrated by the digital integrator137, and then converted into an analog signal Vint by use of the DAconverter 138 b.

Here, in the case of the double-integral AD converter 151, the bandwidthof the above-mentioned feedback can be controlled by variablycontrolling the integration count N1. That is, in an initial pull-inoperation, the value of N1 is set to be a small value so as to reducethe pull-in time of the feedback, while the value of N1 is increased inthe steady operation after the initial pull-in operation is completed,thereby making it possible to realize the robustness in which thefeedback loop does not malfunction by disturbance noise.

FIG. 15 is a circuit configuration diagram illustrating an example of afeedback circuit different from the feedback circuit of the hallelectromotive force signal detecting apparatus according to the presentembodiment as illustrated in FIG. 7. Note that a reference sign 18indicates a fourth transconductance element. The feedback circuitconfiguration illustrated in FIG. 15 does not perform feedback from theoutput signal Vout of the signal amplifier circuit 13, but feedback fromthe input node of the output stage (Gm, out) 135.

That is, it is also possible to provide the fourth transconductanceelement 18 between the output of the third switching circuit 134 and thedifference calculation circuit 15 so as to perform feedback. Anadvantage of this feedback circuit configuration is that the feedbackcircuit for cancelling ripples is insusceptible to the fluctuation ofthe load seen from the output in FIG. 15. However, in the currentsensor, the subsequent stage of FIG. 15 is an output buffer circuitprepared separately, and therefore, such load fluctuation is unlikely tooccur. A disadvantage of the feedback circuit configuration of FIG. 15is that the fourth transconductance element (transistor differentialpair, Gm, 4) is additionally required.

As stated above, the hall electromotive force signal detection circuitaccording to the present embodiment includes a feedback circuit forcanceling a DC offset component to cause ripple-shaped noise in theoutput voltage signal of a signal amplifier circuit. In view of this, itis possible to realize highly accurate magnetic field detection bydynamic offset cancellation means (a spinning current method and achopper amplifier) for modulating an offset voltage of a hall elementand an offset voltage of a signal amplifier circuit, by use of a chopperclock. Further, in comparison with a circuit configuration (e.g., seePatent Document 4) in which filters for reducing ripple-shaped noise areadditionally placed, it is possible to achieve fast response as amagnetic sensor, and further, there is an advantage that no noiseincrease occurs due to the filters thus additionally placed. Further,the above-mentioned hall electromotive force signal detection circuit ofthe present embodiment is usable as a current sensor.

REFERENCE SIGNS LIST

-   1, 11: Hall Element-   2, 12: First Switching Circuit-   3, 13: Signal Amplifier Circuit-   4, 14: Chopper Clock Generation Circuit-   15: Difference Calculation Circuit in Discrete-time (Time    Discretization Difference Circuit)-   15 a, 16 a: Operational Amplifier-   16: Integrating Circuit-   16 a: Operational Amplifier-   17: Third Transconductance Element-   18: Fourth Transconductance Element-   31, 131: First Transconductance Element-   32, 132: Second Switching Circuit-   33, 133: Second Transconductance Element-   34, 134: Third Switching Circuit-   35, 135: Output Stage of Signal Amplifier Circuit-   36: Operational Amplifier-   136: M-bit AD Converter-   138: DA Converter-   138 a: N-bit Register-   138 b: N-bit DA Converter-   150: Time Discretization Difference Circuit-   150 a, 151 a: Operational Amplifier-   151: Double-integral AD Converter-   151 b: Integration Reset Switch-   151 c: Comparator-   151 d: Control Circuit-   151 e: Counter

1. A hall electromotive force signal detection circuit configured tosuppress an offset signal component in a signal composed of a hallelectromotive force signal generated in a Hall element and the offsetsignal component and amplify the hall electromotive force signal togenerate an output signal, the hall electromotive force signal detectioncircuit comprising: a signal amplifier circuit configured to amplify anoutput of the hall element and output a signal having the offset signalcomponent modulated at a frequency of a chopper clock; a differencecalculation circuit configured to sample a component synchronous withthe chopper clock out of an output signal from the signal amplifiercircuit at a timing synchronous with the chopper clock, and output adifference between sampling results at different time; an integratingcircuit configured to integrate an output from the differencecalculation circuit in time domain; and a feedback circuit configured tofeed back an output signal from the integrating circuit to the signalamplifier circuit.
 2. The hall electromotive force signal detectioncircuit according to claim 1, comprising: a first switching circuitconfigured to perform switching operations on terminal pairs of the Hallelement in which a terminal pair for driving a driving current to thehall element and a terminal pair for detecting the hall electromotiveforce signal are interchanged, and to modulate the hall electromotiveforce signal generated in the hall element at the frequency of thechopper clock, wherein: the signal amplifier circuit amplifies an outputsignal from the first switching circuit and modulates the output signalat the frequency of the chopper clock, so that the hall electromotiveforce signal is demodulated to a low-frequency component including adirect current component, and outputs a signal having the offset signalcomponent modulated at the frequency of the chopper clock.
 3. The hallelectromotive force signal detection circuit according to claim 2,wherein: the signal amplifier circuit includes: a first transconductanceelement configured to convert an output voltage signal of the firstswitching circuit into a current so as to generate a first current;resistors configured to perform voltage-division on a component includedin the output voltage signal of the first switching circuit at apredetermined ratio; a second switching circuit configured to invert thepolarity of a voltage generated by the voltage-division according to thechopper clock; and a second transconductance element configured toconvert an output voltage from the second switching circuit into acurrent so as to generate a second current, wherein, the feedbackcircuit includes a third transconductance element configured to convertan output voltage from the integrating circuit into a current so as togenerate a third current, and wherein, with regard to a current sum ofthe first current I1, the second current I2, and the third current I3,the feedback circuit performs feedback operation in which a DC componentincluded in a sum of the first current and the second current in thesignal amplifier circuit is added with the third current such that thecurrent sum becomes zero (I1+I2+I3=0).
 4. The hall electromotive forcesignal detection circuit according to claim 3, wherein: a thirdswitching circuit configured to modulate an input signal at thefrequency of the chopper clock, and an output stage coupled to the thirdswitching circuit are provided in a subsequent stage of the firsttransconductance element.
 5. The hall electromotive force signaldetection circuit according to claim 4, wherein: a fourthtransconductance element is provided between a subsequent stage of thethird switching circuit and the difference calculation circuit.
 6. Thehall electromotive force signal detection circuit according to claim 1,wherein: the difference calculation circuit and the integrating circuitare switched capacitor circuits.
 7. The hall electromotive force signaldetection circuit according to claim 1, wherein: the differencecalculation circuit is composed of an AD converter, and the integratingcircuit is composed of digital circuits.
 8. The hall electromotive forcesignal detection circuit according to claim 7, wherein: the AD converteris a ΔΣ-modulation AD converter.
 9. The hall electromotive force signaldetection circuit according to claim 7, wherein: the AD converter is adouble-integral AD converter.
 10. A current sensor using the hallelectromotive force signal detection circuit according to claim 1.